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Lei Li
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Prepipeline_depth_S and control logic for three iteration cells
1 parent 60dd7ce commit 9325155

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+25
-27
lines changed

2 files changed

+25
-27
lines changed

‎hdl/fpu_div_sqrt_mvp/control_mvp.sv‎

Lines changed: 24 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,6 @@ module control_mvp
148148
/////////////////////////////////////////////////////////////////////////////
149149

150150
logic [C_PC-1:0] Precision_ctl_S;
151-
// logic Full_precision_S;
152151
always_ff @(posedge Clk_CI, negedge Rst_RBI)
153152
begin
154153
if(~Rst_RBI)
@@ -173,8 +172,7 @@ module control_mvp
173172
logic [5:0] State_Four_iteration_unit_S;
174173

175174
assign State_Two_iteration_unit_S = Precision_ctl_S[C_PC-1:1]; //Two iteration units
176-
assign State_Four_iteration_unit_S = Precision_ctl_S[C_PC-1:2]+ {(|Precision_ctl_S[1:0])?1:0}; //Four iteration units
177-
175+
assign State_Four_iteration_unit_S = Precision_ctl_S[C_PC-1:2]; //Four iteration units
178176
always_comb
179177
begin
180178
case(Iteration_unit_num_S)
@@ -249,7 +247,7 @@ module control_mvp
249247
begin
250248
if(Full_precision_SO)
251249
begin
252-
State_ctl_S<=6'h1a; //53+3 more iterations for rounding bits
250+
State_ctl_S<=6'h1b; //53+3 more iterations for rounding bits
253251
end
254252
else
255253
begin
@@ -426,15 +424,15 @@ module control_mvp
426424
case(Precision_ctl_S)
427425
6'h00:
428426
begin
429-
State_ctl_S<=6'h02; //8+4 more iterations for rounding bits
427+
State_ctl_S<=6'h03; //8+4 more iterations for rounding bits
430428
end
431429
6'h06,6'h07,6'h08:
432430
begin
433431
State_ctl_S<=6'h02;
434432
end
435433
default:
436434
begin
437-
State_ctl_S<=6'h02; //8+4 more iterations for rounding bits
435+
State_ctl_S<=6'h03; //8+4 more iterations for rounding bits
438436
end
439437
endcase
440438
end
@@ -461,7 +459,7 @@ module control_mvp
461459
begin
462460
if(Full_precision_SO)
463461
begin
464-
State_ctl_S<=6'h0e; //53+3 more iterations for rounding bits
462+
State_ctl_S<=6'h0d; //53+3 more iterations for rounding bits
465463
end
466464
else
467465
begin
@@ -2877,7 +2875,7 @@ module control_mvp
28772875
case (Precision_ctl_S)
28782876
6'h00:
28792877
begin
2880-
Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+3
2878+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],1'b0}; //+3
28812879
end
28822880
6'h34:
28832881
begin
@@ -2977,7 +2975,7 @@ module control_mvp
29772975
end
29782976
default:
29792977
begin
2980-
Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+3
2978+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],1'b0}; //+3
29812979
end
29822980
endcase
29832981
end
@@ -2987,7 +2985,7 @@ module control_mvp
29872985
case (Precision_ctl_S)
29882986
6'b00:
29892987
begin
2990-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+3
2988+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+3:0],{(C_MANT_FP64-C_MANT_FP16+1){1'b0}} }; //+3
29912989
end
29922990
6'h0a:
29932991
begin
@@ -3247,63 +3245,63 @@ module control_mvp
32473245
case (Precision_ctl_S)
32483246
6'h00:
32493247
begin
3250-
Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+3
3248+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}}}; //+3
32513249
end
32523250
6'h34:
32533251
begin
3254-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+4:3],{(3){1'b0}} }; //Precision_ctl_S+1
3252+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}} }; //Precision_ctl_S+1
32553253
end
32563254
6'h33,6'h32,6'h31,6'h30:
32573255
begin
3258-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64:0],{(4){1'b0}} }; //Precision_ctl_S+1
3256+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-1:0],{(5){1'b0}} }; //Precision_ctl_S+1
32593257
end
32603258
6'h2f,6'h2e,6'h2d,6'h2c:
32613259
begin
3262-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-4:0],{(4+4){1'b0}} }; //Precision_ctl_S+1
3260+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(9){1'b0}} }; //Precision_ctl_S+1
32633261
end
32643262
6'h2b,6'h2a,6'h29,6'h28:
32653263
begin
3266-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-8:0],{(4+8){1'b0}} }; //Precision_ctl_S+1
3264+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-9:0],{(13){1'b0}} }; //Precision_ctl_S+1
32673265
end
32683266
6'h27,6'h26,6'h25,6'h24:
32693267
begin
3270-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-12:0],{(4+12){1'b0}} }; //Precision_ctl_S+1
3268+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-13:0],{(17){1'b0}} }; //Precision_ctl_S+1
32713269
end
32723270
6'h23,6'h22,6'h21,6'h20:
32733271
begin
3274-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-16:0],{(4+16){1'b0}} }; //Precision_ctl_S+1
3272+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(21){1'b0}} }; //Precision_ctl_S+1
32753273
end
32763274
6'h1f,6'h1e,6'h1d,6'h1c:
32773275
begin
3278-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-20:0],{(4+20){1'b0}} }; //Precision_ctl_S+1
3276+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-21:0],{(25){1'b0}} }; //Precision_ctl_S+1
32793277
end
32803278
6'h1b,6'h1a,6'h19,6'h18:
32813279
begin
3282-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-24:0],{(4+24){1'b0}} }; //Precision_ctl_S+1
3280+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-25:0],{(29){1'b0}} }; //Precision_ctl_S+1
32833281
end
32843282
6'h17,6'h16,6'h15,6'h14:
32853283
begin
3286-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-28:0],{(4+28){1'b0}} }; //Precision_ctl_S+1
3284+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(33){1'b0}} }; //Precision_ctl_S+1
32873285
end
32883286
6'h13,6'h12,6'h11,6'h10:
32893287
begin
3290-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-32:0],{(4+32){1'b0}} }; //Precision_ctl_S+1
3288+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-33:0],{(37){1'b0}} }; //Precision_ctl_S+1
32913289
end
32923290
6'h0f,6'h0e,6'h0d,6'h0c:
32933291
begin
3294-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-36:0],{(4+36){1'b0}} }; //Precision_ctl_S+1
3292+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-37:0],{(41){1'b0}} }; //Precision_ctl_S+1
32953293
end
32963294
6'h0b,6'h0a,6'h09,6'h08:
32973295
begin
3298-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-40:0],{(4+40){1'b0}} }; //Precision_ctl_S+1
3296+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(45){1'b0}} }; //Precision_ctl_S+1
32993297
end
33003298
6'h07,6'h06:
33013299
begin
3302-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-44:0],{(4+44){1'b0}} }; //Precision_ctl_S+1
3300+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-45:0],{(49){1'b0}} }; //Precision_ctl_S+1
33033301
end
33043302
default:
33053303
begin
3306-
Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4
3304+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}}}; //+3
33073305
end
33083306
endcase
33093307
end
@@ -3313,7 +3311,7 @@ module control_mvp
33133311
case (Precision_ctl_S)
33143312
6'b00:
33153313
begin
3316-
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+5
3314+
Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+4
33173315
end
33183316
6'h0a,6'h09,6'h08:
33193317
begin

‎hdl/fpu_div_sqrt_mvp/div_sqrt_mvp_wrapper.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ module div_sqrt_mvp_wrapper
8787

8888

8989
generate
90-
if(PostPipeline_depth_S==1)
90+
if(PrePipeline_depth_S==1)
9191
begin
9292

9393
div_sqrt_top_mvp div_top_U0 //for RTL

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