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[None][feat] Add vLLM KV Pool support for XQA mla kernel #8560
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Signed-off-by: Qidi Sang <200703406+qsang-nv@users.noreply.github.com>
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📝 WalkthroughWalkthroughChanges introduce support for a new KV cache layout (PAGED_KV_CACHE_LAYOUT == 1) with separate K/V cache pools, update KV cache indexing and tensor map creation logic, and add CUDA 13.0+ support for memory prefetching and clock rate queries across kernel implementations and test infrastructure. Changes
Sequence Diagram(s)sequenceDiagram
participant Caller as launchMLA Caller
participant Launcher as launchMLA
participant Loader as KVTilePartLoader
participant TensorMap as makeTensorMapForPagedKVCache
rect rgb(240, 248, 255)
Note over Launcher: PAGED_KV_CACHE_LAYOUT == 1 Path (VLLM)
Caller->>Launcher: kCacheVLLM, vCacheVLLM, kvCachePageList
Launcher->>Launcher: Construct KVCacheList from kCacheVLLM/vCacheVLLM
Launcher->>TensorMap: Create tensor maps with kCacheVLLM/vCacheVLLM
TensorMap-->>Launcher: K/V tensor maps
Launcher->>Loader: Initialize with layout 1 baseOffset<br/>(idxReq * maxNbPagesPerSeq)
Loader->>Loader: Load pages with layout 1 indexing
end
rect rgb(240, 255, 240)
Note over Launcher: Legacy Path (Layout 0 or Pool)
Caller->>Launcher: pool, kvCachePageList
Launcher->>Launcher: Construct KVCacheList from pool
Launcher->>TensorMap: Create tensor maps with pool
TensorMap-->>Launcher: K/V tensor maps
Launcher->>Loader: Initialize with layout 0 baseOffset<br/>(formula with beamWidth, 2)
Loader->>Loader: Load pages with layout 0 indexing
end
Estimated code review effort🎯 3 (Moderate) | ⏱️ ~20 minutes The changes span multiple files and introduce conditional logic for two distinct KV cache layouts plus CUDA version-specific paths, requiring verification of indexing formulas and page addressing across both layout branches. However, changes follow a consistent pattern of adding parallel conditional paths rather than heterogeneous modifications, and test file changes are localized to specific CUDA version blocks. Pre-merge checks and finishing touches❌ Failed checks (1 warning)
✅ Passed checks (2 passed)
✨ Finishing touches
🧪 Generate unit tests (beta)
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Actionable comments posted: 2
Caution
Some comments are outside the diff and can’t be posted inline due to platform limitations.
⚠️ Outside diff range comments (2)
cpp/kernels/xqa/test/warmup.cu (1)
7-10: Warmup loop condition is inverted; the loop exits immediately.Busy‑wait should spin until
clock64()reachestic + cycles.Apply:
- while (tic + cycles < clock64()) + while (clock64() < tic + cycles) { }cpp/kernels/xqa/test/test.cpp (1)
569-587: Build break for layout 1 whenUSE_INPUT_KV==1: wrong page list shape and cache array used.This block indexes
pageList[i][0][kv][...]and writescacheHeads[...], but with layout 1 we havepageList[batch][page]and separatecacheKHeads/cacheVHeads. This will not compile whenUSE_INPUT_KV && USE_PAGED_KV_CACHE && PAGED_KV_CACHE_LAYOUT==1.Apply:
#if USE_INPUT_KV @@ - for (int kv = 0; kv < 2; kv++) - { - for (int j = 0; j < nbKHeads; j++) - { -#if USE_PAGED_KV_CACHE - uint32_t const pageIdx = pageList[i][0][kv][pos / tokensPerPage]; - uint32_t const idxHead = tokensPerPage * (nbKHeads * pageIdx + j) + pos % tokensPerPage; -#else - uint32_t const idxHead = maxSeqLen * (nbKHeads * i + j) + pos; -#endif - cacheHeads[idxHead].fill(CacheElem(128.F)); - } - } + for (int kv = 0; kv < 2; kv++) + { + for (int j = 0; j < nbKHeads; j++) + { +#if USE_PAGED_KV_CACHE +#if PAGED_KV_CACHE_LAYOUT == 1 + uint32_t const pageIdx = pageList[i][pos / tokensPerPage]; + uint32_t const idxHead = pageIdx * tokensPerPage * nbKHeads + + (pos % tokensPerPage) * nbKHeads + j; + auto& cacheRef = (kv == 0) ? cacheKHeads[idxHead] : cacheVHeads[idxHead]; + cacheRef.fill(CacheElem(128.F)); +#else + uint32_t const pageIdx = pageList[i][0][kv][pos / tokensPerPage]; + uint32_t const idxHead = tokensPerPage * (nbKHeads * pageIdx + j) + pos % tokensPerPage; + cacheHeads[idxHead].fill(CacheElem(128.F)); +#endif +#else + uint32_t const idxHead = maxSeqLen * (nbKHeads * i + j) + pos; + cacheHeads[idxHead].fill(CacheElem(128.F)); +#endif + } + }
🧹 Nitpick comments (1)
cpp/kernels/xqa/mla_sm120.cu (1)
1973-1980: Scratch layout depends on grid size; ensure caller‑providedscratchis large enough.
cgaXBufandpartialResultsare carved fromscratchusingnbCgas. Consider asserting/ documenting requiredscratchsize to avoid OOB on large grids.
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📒 Files selected for processing (4)
cpp/kernels/xqa/mha.h(1 hunks)cpp/kernels/xqa/mla_sm120.cu(6 hunks)cpp/kernels/xqa/test/test.cpp(6 hunks)cpp/kernels/xqa/test/warmup.cu(1 hunks)
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cpp/kernels/xqa/test/warmup.cucpp/kernels/xqa/test/test.cppcpp/kernels/xqa/mha.hcpp/kernels/xqa/mla_sm120.cu
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cpp/kernels/xqa/test/warmup.cucpp/kernels/xqa/test/test.cppcpp/kernels/xqa/mha.hcpp/kernels/xqa/mla_sm120.cu
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cpp/kernels/xqa/test/warmup.cucpp/kernels/xqa/test/test.cppcpp/kernels/xqa/mha.hcpp/kernels/xqa/mla_sm120.cu
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cpp/kernels/xqa/test/test.cppcpp/kernels/xqa/mha.h
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cpp/kernels/xqa/mha.h
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cpp/kernels/xqa/mha.h
🧬 Code graph analysis (1)
cpp/kernels/xqa/mla_sm120.cu (1)
cpp/kernels/xqa/tma.h (2)
loadAsync(74-129)loadAsync(132-191)
⏰ Context from checks skipped due to timeout of 90000ms. You can increase the timeout in your CodeRabbit configuration to a maximum of 15 minutes (900000ms). (1)
- GitHub Check: Pre-commit Check
🔇 Additional comments (7)
cpp/kernels/xqa/test/test.cpp (3)
82-97: CUDA 13+ managed prefetch API usage looks correct.Using
cudaMemLocationwithcudaMemPrefetchAsync(ptr, size, location, flags=0, stream)is consistent with CUDA 13+. Fallback path retained for older CUDA.Please confirm our CI toolchains define CUDA_VERSION >= 13000 where this overload exists (e.g., R13+). If some builders use older CUDA headers, guard failures could occur.
235-241: KV page list shape and initialization for layout 1 (VLLM) look consistent.
- total pages, buffer sizing, and linear init/shuffle align with
[batchSize][nbPagesPerSeq]shape.pageListArgpointers match the expected kernel API per layout.Also applies to: 262-271, 309-336, 339-355
713-717: AlllaunchMLA/launchMHAcall sites are consistently updated; no additional action needed.Verification confirms both call sites (lines 713-717 for
launchMLAand lines 759-763 forlaunchMHA) correctly pass separate K/V cache heads (cacheKHeads.get(), cacheVHeads.get()) underPAGED_KV_CACHE_LAYOUT == 1, falling back to the single pool otherwise. Both match the function signature expectations inmha.hlines 174-176, where layout 1 expects two separate parameters (kCacheVLLM,vCacheVLLM). No inconsistencies found.cpp/kernels/xqa/mla_sm120.cu (3)
115-119: Correct base offset for layout 1 inKVTilePartLoader.For VLLM layout,
baseOffset = idxReq * maxNbPagesPerSeqmatches[batch][page]indexing. Good.
1936-1942: HostlaunchMLA: tensor map creation matches layout 1 vs pool paths.Separate K/V tensor maps for layout 1 are correctly used; pool fallback unchanged.
Also applies to: 1962-1971
146-151: No issues found—tensor map dimension orders are correctly matched to TMA loads.The verification confirms that both layout branches correctly map dimension indices to tensor coordinates:
- Layout 1:
{idxElemBeg, idxHeadGrp, offset, pages[i]}→ tensor dims{headElems, nbKHeads, tokensPerPage, pageId}✓- Layout 0:
{idxElemBeg, offset, idxHeadGrp, pages[i]}→ tensor dims{headElems, tokensPerPage, nbKHeads, pageId}✓Both single-page (lines 146–151) and multi-page (lines 160–167) cases are consistent with their respective tensor map encodings in
tensorMap.cpp.cpp/kernels/xqa/mha.h (1)
172-180: All function signatures match between declarations and definitions.Verified that
launchMLA,launchMHA, andlaunchHopperF8MHAhave consistent signatures across all files:
- launchMLA: mha.h:168 matches mla_sm120.cu:1874
- launchMHA: mha.h:88 matches mha.cu:2680
- launchHopperF8MHA: mha.h:128 matches mha_sm90.cu:3225
All three functions correctly use the same conditional structure for
PAGED_KV_CACHE_LAYOUT==1(takingkCacheVLLMandvCacheVLLMparameters) versus Layout 0 (takingpool). The public API extension is properly implemented.
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PR_Github #22115 [ run ] completed with state |
Signed-off-by: Qidi Sang <200703406+qsang-nv@users.noreply.github.com> Signed-off-by: yufeiwu-nv <230315618+yufeiwu-nv@users.noreply.github.com>
Signed-off-by: Qidi Sang <200703406+qsang-nv@users.noreply.github.com>
Signed-off-by: Qidi Sang <200703406+qsang-nv@users.noreply.github.com>
Signed-off-by: Qidi Sang <200703406+qsang-nv@users.noreply.github.com>
Signed-off-by: Qidi Sang <200703406+qsang-nv@users.noreply.github.com>
Summary by CodeRabbit
New Features
Refactor
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Description
Add vllm kv layout for xqa mla kernel. Also add support in xqa unittest for cuda version >= 13.0.
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Please review the following before submitting your PR:
PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.
PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
Test cases are provided for new code paths (see test instructions)
Any new dependencies have been scanned for license and vulnerabilities
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Documentation updated as needed
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Please check this after reviewing the above items as appropriate for this PR.
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