透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

DLD Project - A simple vending machine simulation with Verilog (Spring 2024)

32-bit Divider circuit implemented using Verilog

Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.

基于Nexys4开发板和PS2通信协议的键盘设计的电子琴，能够支持24个音阶的弹奏。

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

sequence detector with overlapped 2 patterns 010111 or 1101

This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.

베릴로그 텀 프로젝트: 추상전략게임인 tic tac toe를 구현합니다.

Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.

🎓💻University of Tehran Digital Logic Design Lab Course Projects - Spring 2021

A reliable drone flight data recorder designed with FPGA logic to capture and store real-time trajectory (x,y,z) and attitude (Roll, Pitch, Yaw) data.

EECS207001

11020EECS101002

Joystick enabled Multiplayer Chase Game - An alternate world of Pacman

Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

A A collection of Verilog/SystemVerilog projects developed for the DE10-Lite FPGA board using Intel Quartus.

Digital logic 📐 assignments for module: CSU11026

Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

digital-logic