Questions tagged [ddr]
Double Data Rate describes a computer bus that transfers data on both the rising and falling edges of the clock signal. Often used to describe SDRAM access.
155 questions
1
vote
0
answers
53
views
How to generate true DDR output with OSERDES2 in Spartan-6 without an external high-speed clock (BUFIO2 not possible)?
I’m working on a Spartan-6 design where I need to generate DDR output data using OSERDES2, but I don’t have an external high-speed clock available.
Here’s my setup and the challenge I’m running into:
...
- 73
0
votes
1
answer
49
views
How to interface ADA4355 ADC with Spartan-6 SLX9 FPGA (16-bit DDR/SDR modes)?
I'm working on capturing ADC data from an ADA4355 using a Spartan-6 LX9 FPGA.
According to the ADC datasheet, it can output data in several modes, such as:
16-Bit DDR/Single Data Rate (SDR), Two-Lane, ...
- 73
0
votes
1
answer
52
views
LPDDR4 T Branch topology layout routing length match
For LPDDR4 T Branch topology layout routing do I need to match the length of Level 1 branch also with A0 with other address group like A1 A2 etc should be also equally length match.
Level 1 branch ...
- 169
5
votes
2
answers
867
views
Why does ECC add 1/4 more DRAM ICs with DDR5, rather than 1/8?
While shopping for 32 GiByte DDR5 ECC UDIMMs, I found pictures with 20 identical DRAM ICs, where I was expecting 18, because that's been the usual number for large DDR/DDR2/DDR3/DDR4 ECC UDIMMs, and I ...
- 2,085
0
votes
1
answer
72
views
What is the critical gap for splitting the reference plane - Length matching
Assume you want to route a LPDDR4 memory. You enter a situation were you cannot no longer proceed because there is a via blocking your path. So you decide to remove that via and route your trace.
But ...
- 1,466
2
votes
1
answer
140
views
How do I pass a clock signal through an FPGA while redriving it?
I would like to "pass through" a clock signal in an FPGA, while redriving it.
I would also like to calculate other signals synchronously with the clock and output them (to be sampled on ...
- 631
3
votes
2
answers
547
views
How does Memory Controller in X86-64 CPU Address a 64-bit Integer using 64-bit Address?
Intro
I've watched the channel BranchEducation's video about Computer Memories, and read the first few sections of What Should Every Programmer Know About Memory to understand the memory internals.
I ...
0
votes
0
answers
120
views
How are multiple DDR5 DIMMs wired into to the same channel?
This question is about how multiple DDR5 DIMMs in the same memory channel are wired to the processor. This is mostly an electrical engineering question, and the goal to answer this question:
Will re-...
- 2,268
0
votes
1
answer
150
views
DDR with ARTIX 7 is not initialaizing
We are using Artix7 200T in our design.
We are using two independent DDR3L (MT41K512M16VRP-107 AAT) interface in our card.
Both with 8Gb capacity with 16 bit data width.
Both DDR is completely ...
user398283
0
votes
1
answer
376
views
Ferrite bead vs feed through capacitors for LPDDR4
I am designing a TI's AM6442 processor board
I am using SK-AM64x their development board as desgin reference.
There are two version an older and a newer
Old version schemtatic:
New version ...
- 529
6
votes
2
answers
465
views
LPDDR4 layout, should we avoid having signals in same byte group on different layers?
Is it a bad idea to route intra byte DQx on different layers?
I am trying to interface AM6442 to LPDDR4 16bit. I have followed every constraint in TI's DDR layout guidelines to the letter, ...
- 529
3
votes
3
answers
437
views
Is my meander a bad idea?
Autodesk Eagle's Meander:
My compact meander:
How bad of an idea is it to use "My compact meander" meander instead of the Eagles's version? The Autodesk Eagle's meander tool is very bad, ...
- 529
2
votes
2
answers
818
views
Benefit of bank groups in DDR4 and beyond
I'm trying to understand how grouping the banks together can increase the throughput of DDRx. Reading into the sense amplifier appear to be the main bottleneck in DDRx throughput, however there is ...
- 41
1
vote
1
answer
174
views
How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
- 33
-1
votes
1
answer
127
views
How can autorouting be done in Altium CircuitMaker?
I need to do autorouting in Altium CircuitMaker. I have only found information how to do autorouting in Altium Designer.
What I need to know is to set up rules and enviroment for autorouting with the ...
- 1,466
1
vote
1
answer
83
views
DDR3 U-DIMM Signal Reference Plain
I am doing the PCB layout of a DDR3 U-DIMM and I have run into a perceived gap in the JEDEC DDR3 DIMM standards and am hoping to get some input from a DDR3 SME who could clarify the Address/Control ...
- 37
0
votes
0
answers
35
views
DDR Data strobe wiring
I have a device that has a unified memory architecture and has four 32bit ddr ram chips totaling 128bit and only has a single data strobe for the whole 32bit address bus on each chip not for each byte ...
4
votes
2
answers
679
views
Picking the best memory technology for our needs
We are in the process of figuring out which memory option would be the best for our needs. What are our requirements? Very simple
Bandwidth: BW TB/s, say greater than 20TB/s
Capacity: C TB, say 20TB
...
- 282
1
vote
2
answers
2k
views
What is the fastest achievable output speed for an FPGA?
To sum up the question, I would like to know what is the maximum frequency with which I can toggle an output of an FPGA. I do not intend this question to be specific to any particular board or vendor. ...
- 555
0
votes
0
answers
115
views
DDR pin swaping why D0, D8, D16, D24, D32, D40, D48, and D56 are fixed
Below image is taken from Hardware Development Guide
for i.MX 6SoloLite
Applications Processors.
You can see that in each byte lane first and last bit are fixed.You are not allowed to swap.
May I know ...
- 4,055
0
votes
1
answer
358
views
What is the definition of DDR memory latency?
On Corsair's web site, they define memory latency with an equation:
(Real Latency) = CAS Latency x 2000 / Data-rate
My question is what that means in practice. Is this the delay from the time the ...
- 1,711
3
votes
3
answers
1k
views
For DDR4 and DDR5, is tCCD_l timing to be obeyed for accesses in a single row as well?
So I have been trying to learn about DDR4 and DDR5 memories, and it seems that the Column-to-Column delay values (in clock cycles) are different depending on whether consecutive accesses are inter-...
- 343
0
votes
1
answer
2k
views
DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?
While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock.
The characteristic of DDR is that it transfers 2 sets of data every cycle.
Therefore, for older versions of ...
- 1
0
votes
2
answers
282
views
What are the options to interface Altera or Xilinx FPGA with a microprocessor or microcontroller?
I am trying to design a system which has some sensors connected to an FPGA and want to transfer the sensor data from the FPGA to a microprocessor like NXP IMX. I am new to FPGA and would like to know ...
- 87
0
votes
0
answers
136
views
Mark Horowitz Computing's energy problem - methodology
I have a question about the Mark Horowitz paper: Computing’s Energy Problem
(and what we can do about it). In the paper, the author breaks down the sources of energy loss in modern computing systems.
...
- 41
2
votes
1
answer
176
views
Why is there a tRRD in DDR3? There does not seem to be a resource conflict between different banks
In DDR3, bank activation is specific to the Bank, for different banks, they all have their own sense amp and do not seem to affect each other, so why would there be tRRD?
- 21
-1
votes
1
answer
180
views
DAC DDR Interface with Vivado and Zynq7000
i need to connect a dual-channel DAC (AD9117) to a Zynq 7000 FPGA. The DAC has a DDR Interface, on which the Data for Channel 1 is clocked on the rising edge and the data for channel 2 on the falling ...
- 19
0
votes
2
answers
346
views
Is there any chance to embed two DDR IP cores into FPGA so that I can implement dual-channel memory architecture?
What I want is to implement a dual-channel memory architecture on a FPGA development board and verify that it is really faster than single channel.
At first I was thinking of configuring on-board DDR ...
- 21
2
votes
1
answer
781
views
Why is the DDR termination voltage half the supply voltage? [closed]
Why is the DDR termination voltage (VTT) one-half the VDD voltage?
- 4,055
3
votes
1
answer
963
views
Why is the burst order of DDR3 DRAM not sequential?
Based on the JEDEC DDR3 documentation as shown below, when we are reading with burst length of 8 and starting column address of 010 (0x2), the burst order will be <...
- 1,104
1
vote
1
answer
135
views
Does JTAG use DDRAM?
I have a microcontroller with external DDRAM. When I debug with JTAG I can see that there is code placed in the DDRAM region. However I never see the initialization of DDRAM code is run. I wonder does ...
- 11
1
vote
0
answers
3k
views
What's the purpose of the DDR4 1X, 2X and 4X refresh modes?
The DDR4 specification defines 1x, 2x and 4x refresh modes as follows:
The default Refresh rate mode is fixed 1x mode where Refresh commands
should be issued with the normal rate, i.e., tREFI1 = ...
- 431
1
vote
2
answers
4k
views
What is mean by VREF Training in DDR4?
While going through DDR3 and DDR4, there is a term called vref. Where in DDR3 it is outside the DDR and for DDR4 it is inside the chip. Why we need training for it. What is the use of it.
- 563
2
votes
1
answer
409
views
Length matching on DDR3 dataline in simulation for STM32MP1
I'm using HyperLynx to emulate my STM32MP157AAA3 small form factor system board with DDR3-1066 memory.
When I use DDRx batch simulation:
I confirmed that my ODT model is configured correctly. Use 48 ...
- 23
3
votes
0
answers
446
views
DDR Trace Length in Motherboards
I was trying to understand DDR, Trace-length, and signal integrity.
Most of the datasheets, For example, iMX8M Mini (Doc: IMX8MMHDG) clearly specifies what are the requirements for the each signal in ...
3
votes
1
answer
359
views
Why did GDDR5X implement QDR?
DDR makes complete sense to me: it matches up the transition rate between the data signals and clock, so that twice the data can be sent over a bus without increasing the overall design bandwidth. The ...
- 11.5k
13
votes
1
answer
2k
views
Why was full page bursting removed when we moved to DDR
I'm interfacing with SDRAM on an FPGA and full page bursts are a godsend for streaming data. It's seems to be much, much more handy then a fixed burst size. I know it was removed when we moved to DDR. ...
- 225
0
votes
0
answers
72
views
How do I find out what pins of an Intel FPGA can be used to connect to different pin groups in EMIF?
If I want to connect my Intel FPGA using EMIF to a high speed DDR Memory e.g Cyclone IV E to DDR3 memory or Max 10 to DDR2 memory, how do I find out what pins can be used for the data, strobe, clock, ...
- 12.4k
4
votes
0
answers
146
views
Can I use LPDDR3 memory that is larger than my processor supports?
I am working on a thing that uses a STM32MP157C. Its datasheet says:
The STM32MP157C/F devices embed a controller for external SDRAM which support the following devices
• LPDDR2 or LPDDR3, 16- or 32-...
- 141
1
vote
1
answer
632
views
How much skew correction can typically be applied to DQS during DDR4 link training?
My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync.
Is there ...
- 11.5k
1
vote
0
answers
33
views
DDR interfacing with rockers3399 processor
I am using rockers 3399 processor in one of my applications. if you see page no 9 'External Memory or Storage device' section you can see the below things
*Support 2 channels, each channel is 16 or ...
- 4,055
0
votes
2
answers
1k
views
LPDDR: is pluggable (socketed, not soldered) connection possible for low voltage?
I've already asked the question about plausibility of socketed LPDDR here and got an answer LPDDR on separate replaceable modules / boards - possible? drawbacks?
You could probably extend LPDDR onto ...
- 275
0
votes
0
answers
167
views
How many DDR memory chips can be connected to Zynq UltraScale+ MPSoC ZCU104
I have a question regarding Zynq UltraScale+ MPSoC: how many DDR RAMs can be connected to the ZU7EV device, including both PS and PL banks ?
Here is the link for TRM.
- 1
-2
votes
1
answer
491
views
Additive latency for DRAM READ and WRITE commands [closed]
In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
- 423
0
votes
1
answer
440
views
LPDDR on separate replaceable modules / boards - possible? drawbacks?
I've read that LPDDR is more efficient in active states and times more energy efficient than DDR in inactive states, e.g. in Performance vs power in off-chip DDR SDRAM, there is a mentioning of ...
- 275
3
votes
3
answers
2k
views
maximum memory supported by processor - why often stated less than 1TB?
I want to understand technical details of limitations of maximum memory size a system / processor can support. Below what I was able to find via web search to date Wiki:
Modern 64-bit processors such ...
- 275
2
votes
1
answer
245
views
DDR4 Routing Consideration
I'm designing a new PC based on Intel Tiger Lake UP3.
In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2).
each BO has different impedance ...
- 1,107
1
vote
1
answer
323
views
DDR3 logic levels - AC or DC?
In a DDR3 datasheet, I found different voltage levels (AC and DC.) I already know about DC logic levels but I don't know about AC logic levels.
What is the difference between the two?
Do the AC values ...
- 4,055
0
votes
0
answers
359
views
Timing Diagram - HyperBus - HyperFlash - HyperRAM - RWDS - CLK - DQ
I'm trying to design an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK ...
- 1
0
votes
1
answer
299
views
Is data width of an external DDR memory the same as the pins used to transfer data?
I'm trying to configure a Memory Interface Generator IP in Vivado. Somehow, the Block Automation doesn't work and I've to do it myself.
The board I'm using is the Arty A7 development board. It has a ...
- 237