Questions tagged [fpga]
A Field-Programmable Gate Array (FPGA) is a logic chip consisting of an array of programmable logic blocks and interconnects that is configured by the customer after manufacturing—hence "field-programmable".
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OLED drive FPGA MIPI DSI?
I have found an OLED display on AliExpress. I have tried to find another one but this is the only one I have found with the dimensions I need, I have a proprietary video signal and need to make an ...
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How to generate true DDR output with OSERDES2 in Spartan-6 without an external high-speed clock (BUFIO2 not possible)?
I’m working on a Spartan-6 design where I need to generate DDR output data using OSERDES2, but I don’t have an external high-speed clock available.
Here’s my setup and the challenge I’m running into:
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On ECP5, which power pins are utilized by differential pairs?
On ECP5, which power pins are utilized by differential pairs?
Last time I checked, the datasheet is not really clear on whether the differential outputs (LVDS) are powered by VCCAUX or VCCIO. It could ...
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Decoupling/bypass strategy for EPC5 FPGA BGA with only top layer assembly?
To be specific about the part, it is LFE5U-45F-8BG381C in 381-FBGA.
I have at least one ground plane and two power planes (one for VCCIO and one partitioned for VCC and VCCAUX).
However I want to ...
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How to interface ADA4355 ADC with Spartan-6 SLX9 FPGA (16-bit DDR/SDR modes)?
I'm working on capturing ADC data from an ADA4355 using a Spartan-6 LX9 FPGA.
According to the ADC datasheet, it can output data in several modes, such as:
16-Bit DDR/Single Data Rate (SDR), Two-Lane, ...
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PolarFire PF_RAMS memory init fails: “sNVM page insufficient” when initializing 3 SRAM IPs — how to force init into LUT/BRAM instead of sNVM?
I have a Microchip / Microsemi PolarFire FPGA design built in Libero where I instantiate a RISC-V core (System Builder) and three additional PF_RAMS (PolarFire SRAM) IP blocks that I want to ...
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Spartan-3A - GCLK vs LHCLK vs RHCLK
What is the difference between the GCLK vs LHCLK vs RHCLK on a Spartan-3A FPGA? From the “Spartan-3A FPGA Family” datasheet I found the below description.
The “GCLK” global clock inputs can optionally ...
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Push-pull along with pull-up
A FPGA I/O is connected to the OE# of a transceiver and I want to ensure that OE# is high (>=2V) when the system powers up and until the FPGA is configured. The system is battery powered and the ...
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MIPI to SPI conversion doubt
This is going to a very oversimplified post
This is about interfacing a camera sensor to a fpga and I'm a newbie.
Short question : I have this FPGA, and this camera, how do I interface them?
Sub-...
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CRC decoder and determining the number of error bits
I am building a hardware parallel crc_6 encoder and decoder. The polynomial I am using with the given length of input data has HD=3, meaning it can detect up to 2 error bits. The flow is at the ...
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Generating LVDS clock on Cyclone IV E (M25/M26 pins)
I’m trying to generate a clock for an external ADC using a Cyclone IV E (EP4CE115F2907N) on a Terasic DE2-115 board. I connected the PLL output to pin M25, which I configured as LVDS in Quartus. ...
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Why are current limiting resistors enough for interfacing this PS/2 port to this FPGA?
On this Digilent/Xilinx Spartan 3e 1600 FPGA board, they use 270 ohm resistors as current limiting resistors.
In their guide they state:
The PS/2 port on the MicroBlaze Development Kit board is ...
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Timing violations from reset - Libero
I am doing a project consisting of all Microchip IP (PCIe endpoint, DDR4) and am getting 501 timing violations that all have the launch point of DFF15[0]:CLK which is the output of the CORERESET_PF ...
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Series termination placement next to receiver
I have series termination resistors very close to the receiver, I have realized that they must be next to the driver (can't be moved since Im using a SOM).
The parallel HDMI input signals that go into ...
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Can I do multi bit CDC using synchronizers without handshake or FIFO?
I know that asynchronous FIFO and handshake can do CDC, but the FIFO consume more resource, and handshake is a little complicated.
If I have a multi bit signal "src", and it vary slowly, I ...
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Using LUT RAM for an array of structs in Vivado
I'm trying to synthesize the following hardware in Vivado, which contains an array of my_struct_t. To reach timing closure, it's important that this array is ...
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Can the Waveshare USB3300 5V Pins damage an FPGA
I am trying to connect the Waveshare USB3300 extension board to an FPGA. https://www.waveshare.com/usb3300-usb-hs-board.htm . The datasheet is https://www.waveshare.com/wiki/File:USB3300-USB-HS-Board-...
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LCMXO640C-3TN144C Maximum Clock Frequency
I am a beginner with FPGAs and I want to find what is the maximum clock frequency where the I/O pins and PCLK pins of this FPGA "LCMXO640C-3TN144C" can work with.
MachXO Family Data Sheet ...
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What's the difference between 'EXTRACT_ENABLE' and 'DIRECT_ENABLE'?
Both attributes are used to tell Vivado if we want to use the enable pin of a DFF. What's the difference between them? When is one more preferable than the other?
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How blocking assignment affect non-blocking assignment in Verilog?
module t;
reg a;
initial a <= #4 0;
initial a <= #4 1;
initial $monitor ($time,,"a = %b", a);
endmodule
Output of above Verilog code is:
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Which family of FPGA to choose [closed]
I am embarking on a new project to replace simple scanning circuits. Previously this was done with a couple of 8 bit counters linked by glue logic, then driving multiplying DACs and other analog ...
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What’s the recommended workflow to implement an FSM in Verilog and generate waveforms in Intel Quartus? (Beginner question)
I’m a complete beginner in FPGA and HDL design, and I’m starting a small project to control a 4-floor elevator using a finite state machine (FSM). My ultimate goals are:
1. Derive the equivalent logic ...
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Ethernet GMII MAC to MAC Loopback
I am trying to connect two MACs in GMII mode - using a SoC to connect them, and routing GMII signals through the Fabric.
In the spec for the Intel MAC GMII IP, it assumes connection to PHY.
This IP ...
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Interfacing ADS1115 ADC with Microchip PolarFire SoC Discovery Kit
I have been trying to connect the ADS1115 ADC with my Microchip PolarFire SoC discovery kit FPGA board, I have written the FSM for I2C master by collecting the code from various sources because I am ...
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How to open the precompiled Quartus Prime project
I have precompiled (with db and incremental_db folders, so it have sof/pof files) Quartus Prime (22.1std.1 Build 917 02/14/2023 SC Lite Edition) project and want to open "Technology Map Viewer (...
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Why is Vivado connecting this reset to the CE pin when the R pin is available?
Vivado is connecting up the reset signal through a LUT to the CE pin of the FDRE, even though the R pin is available. This is a 2k signal, and it's using up 2k LUTs to do this, unnecessarily. Any ...
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How to achieve the lowest latency when sending and receiving data between a Linux server and an FPGA?
I am working with a Xilinx Alveo U50 FPGA and have developed an FPGA program for model inference. However, I am encountering a bottleneck in data transfer latency between Linux and the FPGA.
Currently,...
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When would we like to use a resistor here?
In Xilinx's 7 Series FPGAs Configuration User Guide (UG470), they say
M[2:0] determine the configuration mode. Connect each
mode pin either directly, or via a ≤1 kΩ resistor, to VCCO_0 or GND.
Adding ...
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Sending a signal to ESP32 through an FPGA using I2C protocol
I want to send a signal to ESP32 through an FPGA using I2C protocol, and I have got a problem:
Can I use the ESP32 WROOM, for example? Does it have the same reg with the same purpose as in this manual ...
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Sending 20 MHz Square Wave using a FPGA
I have an Arty S7-50 FPGA board. I created a state machine on the FPGA. In certain states, I send a 20 MHz square pulse through the IOs. The flip-flop outputs are connected to the IO via OBUF. After ...
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How to take a signal from GPIO pin and feed to a device with SMA input
A PCB with an FPGA is generating a pulse which is available on a JST connector GPIO pin. It is approx 30 ns wide, and repeats approx every 40,000 ns. The device for which this signal is destined has ...
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Is my Finite State Machine Moore or Mealy?
Can someone please tell me whether the following FSM that I designed is Moore or Mealy? It is a UART Transmitter.
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Best approach to design overcurrent monitor circuit
I have some power coming into my design, let's say 50V. I need to design a simple current monitoring (overcurrent) to detect if there is any overcurrent condition then disconnect the 50V to my load ...
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Unable to control IIC sensor using JTAG to AXI Master and AXI IIC Xilinx IPCore
I'm trying to communicate with a temperature sensor (TMP461) without using the PS, relying solely on the Programmable Logic. For this purpose, I'm using JTAG to AXI bridge and the AXI IIC IP provided ...
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Issue VHDL custom AXI4-STREAM IP generating TLAST
I'm currently debugging a custom AXI4-Stream RTL module that I'm using to transfer data from the XADC to the DMA on a Zynq SoC. The goal of this module is to collect a fixed number of samples (...
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SDRAM to OCM via DMA on the Agilex 5
I am in the process of learning about communication between SDRAM and OCM via DMA, using the Agilex-5.
The idea will be to write 0xdeafbeef to the SDRAM, then ...
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FPGA - Designing a parallel scrambler that also unscrambles to return original data
More details given below. My main question is, should the scrambler return the original data if the scrambled input is passed back into it? And if yes, what logic am I missing?
Apologies for the poor ...
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FPGA metastability when going from a slow clock to faster clock?
I am new to FPGA, and I keep reading articles about how it is critical to double flop any sampled signal when going from a slow clock domain to a fast clock domain...
https://nandland.com/lesson-14-...
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XCE04S2-10FFG668C Datasheet
I have the "XCE04S2-10FFG668C" xilinx FPGA but I can't find the datasheet of it. Do you know where I could a datasheet or a pinout diagram at least?
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Using a non-clock pin to drive sequential logic on Artix7
I have a design where an SPI CLK comes in on a non-CCIO pin. I can not change the pin. The FPGA is an Arty7.
I am looking for ways to still drive sequential logic from this pin. I understand that this ...
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PCIe End-Point P2P communication via Root Complex
I have two FPGAs which have PCIe gen3 x16 ports which are connected to the same root complex (and the host). I have been trying to find a way to achieve "root complex routed"/direct DMA ...
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Risetime of DDR3 clock signal AMD Xilinx
I am using ZYNQ7010 SoC from Xilinx (AMD) to control two DDR3 memories with fly by routing. I am trying to run simulation to check signal integrity overall. Where can I find risetime information for ...
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JTAG Not Working On TE0720/TE0706/TE0790-03
I am a uni student familiar with xilinx products and I have never used trenz electronics but I can't seem to establish a connection through jtag using the trenz electronics te0720 with the te0706 ...
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PCA9540 for voltage level translation
I'm trying to use the PCA9540B as a MUX and as a voltage level translator, but the datasheet is confusing me a bit. It says:
"If the PCA954X is supplied with 3.3 V, it will clamp the voltage to ...
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PIR Motion Sensor and BASYS 3 FPGA Connection
I have been trying to create a project of adaptive light brightness using BASYS 3 FPGA and a PIR Motion Sensor HC-SR501. I connected the output of the motion sensor to a PMOD pin in the BASYS 3 to ...
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FPGA stops communicating when power cycled
I'm working with a Lattice FPGA (LCMXO2-1200HC-4TG144C) and a program that has always worked until now. This problem is driving us nuts.
Recently, I made a new PCB with a new FPGA and other components....
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Debounce pushbutton on FPGA by using two D Flip Flop
I'm designing a module debounce pushbutton that uses 2 D Flip Flops and a Slow Clock (4Hz) and an AND Gate(Output) to ensure that the signal will generate with a single pulse. I have learned this ...
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Why do they need so many capacitors here instead of one single capacitor?
In this video, there are many capacitors in parallel in the schematic. What downside would we have if we calculate the equivalent capacitance and replace them with one capacitor?
The only possible ...
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