Questions tagged [fpga]
A Field-Programmable Gate Array (FPGA) is a logic chip consisting of an array of programmable logic blocks and interconnects that is configured by the customer after manufacturing—hence "field-programmable".
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Strange artefacts on LCD display being driven by FPGA
I'm trying to use a Tang Nano 9K FPGA to generate a good signal for a 4.3 inch LCD display with a 40-pin connector.
If I display a checkerboard image like this
then all is well.
This code generates ...
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What is the relation between number of LUT values and output frequency?
VLSI/FPGA beginner here.
I interfaced my Digilent Arty A7-35 with a DAC, using basic DDS (implementing timing diagram of the DAC on FPGA) and interfacing LUT(s) to form sine waves of multiple ...
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Encryption of Verilog/VHDL module
I don't have encryption licenses for Vivado or Quartus to encrypt my Verilog/VHDL modules and so I cannot give my RTL to any user. I don't want to give out synthesized netlists but only encrypted RTL.
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Packaging synthesized design as netlist for use in future designs
I am attempting to create a synthesized netlist of an FSM to help decrease my synthesis time, but I've been unable to get Quartus to generate the correct output files or even find any resources on ...
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How to see the connections of each flip-flop in Vivado RTL schematic view?
I am trying to make the design shown below which is basically a shift register:
When I elaborate this design in Vivado, it shows me the following:
How can I see which flip-flops the inputs and ...
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Adding VHDL DDR Memory Interface IP to block design in XIlinx Vivado
I am using a Nexys A750T FPGA dev board and I would like to use the onboard DDR2 SDRAM. When I attempt to generate the MIG 7 series IP via the IP catalog, the IP wizard forces the design to be in VHDL ...
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How do I initialise an Unpacked array in Verilog?
I need to initialize multiple lookup tables, for which I need a 12-bit array of possibly many indexes. An example:
reg [11:0] address[1:0];
For this, how do I ...
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How to set a testbench file as top level entity ? [Vivado, Basys3Artix7]
This is the first time I use Vivado.
I can't set test_mySWLED.v as Top
I Run Behavioral Simulation
End up with mySWLED waveform instead of test_mySWLED waveform.
Here is my project: https://...
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How do I call a module repeatedly in Verilog, in sync with a clock?
What I intend to do is basically cycle through a LUT created in a second module, by instantiating it in the first. Additionally, I need to call the instantiation in sync with the clock.
The basic idea ...
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SDRAM logic makes noise on ADC readings with FPGA
I am working on a design in which an FGPA reads the output of a 12-bit 40MHz ADC and then stores half of the data on an external SDRAM and the other half on an on-chip BRAM after some averaging.
The ...
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FPGA sync reset with filtering
I have been reading about FPGA reset strategies. One thing that it appears all can agree on is that the reset release should be synchronous with the system clock. For reset assertion, the opinions are ...
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Channel-style routing on Altera FPGAs
A Tutorial on FPGA Routing claims that there are two different FPGA routing styles; channel-style ASIC routing and island style routing:
Academic research has adopted as FPGA architecture a ...
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Can I drive LVCMOS12 on Xilinx Artix-7 at 100 Mbps?
I'm currently planning a setup as shown below, where I need to operate the GPIO on my chip at a data rate of 100 Mbps. My biggest concern is whether it is a feasible to drive LVCMOS12 on Xilinx Artix-...
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Why are the lookup tables in FPGAs small?
An FPGA can be seen (visually at least) as a matrix of cells. Each cell has a LUT (look-up table) inside, implemented with SRAM and MUX.
Why does the size of such a LUT (and hence of the SRAM) need to ...
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Populating BRAM using a .coe file on Xilinx Alveo U280
I am new to the world of FPGAs.
I am using Xilinx Alveo U280. While performing a task in my research project, I tried to populate the BRAM with 0's but the simulation shows 'Z', 'ZZ', and 'ZZZZ' as ...
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Vivado Ethernet IP core licensing issue
I have a PL design in which I included a 10G/25G Ethernet Subsystem IP core from Xilinx configured with BASE-KR, AN/LT logic and FEC logic for Clause 74. When I try to generate the bitstream, I am ...
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DE10-Lite VGA Controller Display
this is my design: https://github.com/Shehab-Hesham/FPGA_IP_VGA/tree/main.
On an oscilloscope, the vertical sync and horizontal sync are correctly given as output; however, the color channels output 0 ...
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How to set I/O constraints when the device is clocked by the FPGA
What is the proper way of setting I/O constraints when the device is clocked by the FPGA?
As an example schematic is given below:
The ADC is clocked from the FPGA. I have generated_clock constraints ...
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Pulse-per-second (PPS) Interface to FPGA
I am currently working with RFSoC 4x2 boards to implement a network of SDRs and require synchronization across multiple boards to a time reference. I plan to utilize the pulse-per-second (PPS) signal ...
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Connecting cross referenced nets to inout ports in verilog
I am prototyping an ASIC on Xilinx FPGA, which has a third party DDR interface. In order to implement the design, the ASIC DDR controller is replaced with a Xilinx DDR4 controller. This controller ...
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PSL usage in Formal Verification, assertion problem
I am investigating the usability of formal verification in FPGA designs using VHDL, PSL, SymbiYosys, and GHDL. I've watched several webinars, read a PSL book, and gone through tutorials. Currently, I ...
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Problems in understanding PCIe blocks in Xilinx Vivado for Versal devices
AR 1215986 was mentioned on page 7 of PG344, Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide.
In this AR, the author mentioned several components, namely:
PCIe PHY
GT QUAD
...
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PMOD I2S2 bit resolution
Im getting a bit confused about the bit resolution I should use with I2S2 Pmod.
It says the max resolution its 24 bit per sample (24 for left audio and 24 for right audio)
But then, they recommend the ...
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What is the fastest achievable output speed for an FPGA?
To sum up the question, I would like to know what is the maximum frequency with which I can toggle an output of an FPGA. I do not intend this question to be specific to any particular board or vendor. ...
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Cross correlation using FPGAs
I have the requirement of performing continuous cross correlation on an incoming signal with a reference signal that is 6000 coefficients large using an Intel FPGA at a data rate of 66 MSPS. One ...
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Is it legitimate to apply reset logic to inputs only?
Let us consider this module for FPGA implementation:
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HDMI output from FPGA
I've got an old project that produces NTSC video output from an FPGA using a resistor ladder DAC. It also produces a stereo audio signal using a similar RL DAC.
I'd like to bring it into the modern ...
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ICM-42688-P read from address not given in Datasheet
I am currently working on software for a project that involves an ICM-42688-P sensor IC.
The FPGA uses a 16-bit SPI interface and needs to read this data block of 16 bytes:
Datasheet Page 60, 13.1
So ...
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Can you simulate a GZK-energy cosmic ray zap to hardware you're simulating?
There have been over a hundred particles of energy 5e19 eV matching the Greisen–Zatsepin–Kuzmin limit detected on Earth since 1991. There has even been a particle supposedly with energy at least 2e20.
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Considerations in board layout for different interface speeds
Currently, I'm working on a design that includes four data buses operating at different datarates.
The signals connect various parts of the system to the central FPGA. I have experience in designing ...
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FPGA output timing explained
As a hardware designer you have consider the timing constraints of both the input and output device. Input devices specify a setup and hold time reference to the clock (the time in which the data ...
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Best way to go from 5V to .95V to power an FPGA at max 15A
I need to power the core voltage on an FPGA from a 5 volt supply with a lot of constraints.
This is a rad hard environment so many components are ruled out. I'm only able to find a SMPS that will go ...
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VHDL modular multiplication always resulting 0 in simulation
I'm trying to implement a modular multiplication algorithm in VHDL, but the result "r" is set to 0 on every simulation. I would like to know how to fix it.
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DDR4 Routing Consideration on pcb (no DIMM)
I need to route DDR4x2(3200MHz) to my FPGA.
my stackup is 12 Layers, TH Via only, and thickness of 2mm PCB.
my question regard which layer to route the FPGA to DDR4, when the two component on the TOP(...
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How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado?
I am new to the field of FPGAs. The FPGA I am using is Virtex-7 VC707 -2 speed grade. In my research project, I am required to reduce the supply voltage (BRAM's specifically) to a low value, say 0.7 ...
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How to properly constrain this hold time?
I am puzzled, can't get to any seemingly simple and, what's more important, solution looking correctly.
There's a main fast clock, fclk, and I divide it by 4, ...
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SPI read of MAX31856 in Verilog
I am trying to read the K-type thermocouple temperature with MAX31856 in Verilog.
Configured the configuration registers CR0 & CR1.
The conversion result is stored in the registers 0xC, 0XD, 0XE. ...
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Unable to write to MT25QU256 from Arria 10 SOM
I am using module Arria 10 SOM by iWave with IC Flash MT25QU256. I am trying to read and write from NIOS II processor to different sectors of this flash.
Currently, I'm using the IP Core Generic Quad ...
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How can I achieve a higher precision than 14-bit in an analog to digital conversion (ADC) [closed]
How can I achieve a higher precision than 14-bit in an analog to digital conversion (ADC) without using conventional ICs on the market?
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ECP5: Determining max current an FPGA pin can sink from datasheet
I have a circuit where I want to drive the CS# input on a SPI flash chip from an output pad on an FPGA. The flash IC's datasheet recommends putting an external ...
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How to get a clean clock signal from FPGA to DACs?
I have the VC707 FPGA board and an external reference clock (fairly clean 100MHz), that I want to use as a reference for a 200MHz generated clock on my board. Then using this clock to clock my DACs (...
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Different ways of fanning out low jitter clock signal
Recently I'm working on a project that involves a FPGA and two high precision DACs.
The DACs require a low jitter 27MHz clock (RMS jitter < 1ps) to function at their datasheet performance.
There is ...
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Verilog variables updated only when assigned as an output
I am facing a strange issue, and I am not sure what is going on here:
assign output_data = {3'b000, cmd_state[1:0], w_data[2:0]};
Where last 5-bits of output data ...
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VHDL schematic without connections [closed]
I'm learning VHDL and I tried to replicate a circuit that I found surfing in internet. The problem is that the schematic shows without connections in the input ports.
The program is a frequency ...
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Is it possible to know through simulation whether we have the right number of decoupling capacitors?
More decoupling capacitors than a certain amount does not improve the power integrity much. I am not sure if this is a case of diminishing returns or a case of reaching a wall.
How exactly can we ...
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Connecting GPIOs on two boards with independent power supplies
I'm trying to design a board that will accept UART/8N1 input from another board at 3.3V. While the two boards share a common GND (obviously), they otherwise have totally independent power supplies: ...
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FPGA clock only positive lag?
I have an FPGA with the following, simple clock divider, written in VHDL:
...
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Verilog- Why is my state machine output arriving one clock cycle earlier?
I'm writing a Verilog code for a state machine with 4 states. state 0 is buffer time of 1 microsecond. state 1 is trig pulse for 10 microseconds. in state 2, the input is read. If the input is high ...
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Proper way to make HDL and timing analyzer understanding the clock slowdowns
This is a question spans two fields - HDL synthesis and timing analysis.
In the design I define clock with specific frequency, and if design has
...
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